AN 798: Partial Reconfiguration with the Arria 10 HPS

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ID 683034
Date 1/25/2017
Public
Document Table of Contents
Document Table of Contents x
Partial Reconfiguration with the Intel® Arria® 10 HPS
Partial Reconfiguration with the Intel® Arria® 10 HPS x
Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Prerequisites for Using This Document x
Knowledge Prerequisites Software Tool Prerequisites Hardware Prerequisites
Partial Reconfiguration Tools and Methods x
Hardware Tools and Methods Software Tools and Methods
Hardware Tools and Methods x
Arria 10 SoC Partial Reconfiguration Support Overview of the Arria 10 GHRD
Arria 10 SoC Partial Reconfiguration Workflow x
Hardware Workflow Software Workflow
Creating the PR Example Design x
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
Qsys Partial Reconfiguration Freeze Logic x
PR Freeze Bridge PR Freeze Controller
Add a Partial Reconfiguration Region to the GHRD x
Creating the Partial Reconfiguration Design Adding the PR Region Connecting New Ports in the GHRD Module Instantiation
Generating the Example Software Image x
Overview of Software Image Creation Generating a New Boot Device Tree Creating the Device Tree Overlays
Generating a New Boot Device Tree x
Critical Information in the Default Device Tree Steps to Create a New Device Tree
Loading Partial Reconfiguration Designs Using Linux x
Installing Files on the SD Card Loading and Unloading the Device Tree Overlays
Partial Reconfiguration with the Intel® Arria® 10 HPS

Importing the GHRD Project

  1. Extract the .tar file provided with the SoC EDS GHRD hardware example, as follows: 
    $ mkdir ghrd_pr 
$ cd ghrd_pr/ 
$ tar xvfz ~/intelFPGA/16.1/embedded/examples/hardware/ \
a10_soc_devkit_ghrd/tgz/ghrd_10as066n2_16_1_*.tar.gz 

(…) 

$ which quartus 
~/intelFPGA_pro/16.1/quartus/bin/quartus 
$ quartus &
  2. Open the GHRD Quartus project file.
  3. Open the GHRD Qsys design saved in the ghrd_10as066n2.qsys file with the Qsys Pro tools. Point to Tools and click Qsys Pro to start the tool.
  4. The copied design is in the standard Qsys tool format and must be converted to the Qsys Pro format. A dialog box confirming this action pops up automatically after opening the Qsys design. Click OK to perform the conversion.
    Figure 5. Converting to Qsys Pro Format
  5. Save the converted design and click Generate RTL to ensure that the conversion process was successful.
  6. Close the Qsys Pro tool.
  7. In the main Quartus window, point to Project and click Revisions. Create a new revision for the PR base configuration. Double click << new revision >> and enter the revision information as shown below. This revision is based on the existing revision.
    Figure 6. Creating the Base Revision
  8. Click OK to create the revision and open it as the current revision.
  9. To set the revision type of the new revision, point to Assignments, click Settings, choose the General category, and change the Revision Type field to Partial Reconfiguration – Base as shown below.
    Figure 7. Setting the Revision Type
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