AN 798: Partial Reconfiguration with the Arria 10 HPS

ID 683034
Date 1/25/2017
Document Table of Contents

Add a Partial Reconfiguration Region to the GHRD

All PR implementation revisions use the top-level placement and routing results from the base revision.

The base and alternate personas are created as separate Qsys modules. As a result, each PR region is a hierarchical logic grouping, which can be designated as a design partition and a LogicLock Plus region. Intel strongly recommends that you follow this practice in your own design, so that there is a clear division between static and dynamic regions.