Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 3 FPGAs and SoCs
                    
                        ID
                        848621
                    
                
                
                    Date
                    4/23/2025
                
                
                    Public
                
            1. Overview
| Updated for: | 
|---|
| Intel® Quartus® Prime Design Suite 25.1 | 
Configuration via Protocol (CvP) is a configuration scheme supported in Arria® V, Cyclone® V, Stratix® V, Arria® 10, Stratix® 10, Cyclone® 10 GX, and Agilex™ FPGAs. The CvP configuration scheme creates separate images for the periphery and core logic. You can store the periphery image in a local configuration device and the core image in host memory, reducing system costs and increasing the security for the proprietary core image. CvP configures the Altera FPGA fabric through the PCI Express* ( PCIe* ) link, and is available for Endpoint variants only.
This document describes the CvP configuration scheme for Agilex™ 3 FPGAs.