Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 1/21/2022
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7.2.1. Active Serial Configuration

Figure 132. High-Level Overview of EPCQ-L Programming for the AS Configuration Scheme


In the AS configuration scheme, configuration data is stored in the EPCQ-L configuration device. You can program the EPCQ-L device in-system using the JTAG interface with the Serial Flash Loader (SFL) IP core. The SFL acts as a bridge in the FPGA between the JTAG interface and the EPCQ-L device. The AS memory interface block in the Intel® Arria® 10 device controls the configuration process.

The AS configuration scheme supports AS x1 (1-bit data width) and AS x4 (4-bit data width) modes. The AS x4 mode provides four times faster configuration time than the AS x1 mode. In the AS configuration scheme, the Intel® Arria® 10 device controls the configuration interface.

Note:

For Active Serial programming using SFL, the MSEL pins must be set to Active Serial setting to allow the programmer to read the EPCQ-L ID.