Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 1/21/2022
Document Table of Contents Delay-Locked Loop

The delay-locked loop (DLL) finds the delay setting for 9 bits delay chain so that the delay of the chain is equivalent to one clock cycle.

Each I/O bank has one delay-locked loop (DLL) located in the center that supports a frequency range of 600 MHz to 1.3 GHz.

The reference clock for the DLL comes from the output of the PLL in the same I/O bank. The DLL divides the reference clock by eight and creates two clock pulses—launch and measure. The phase difference between launch and measure is one reference clock cycle. The clock pulse launch is routed through the delay setting controlled by the delay chain. The delayed launch is then compared to measure.

The setting for the DLL delay chains is from a 9 bit counter, which moves up or down to alter the delay time until the delayed launch and measure are aligned in the same phase. Once the DLL is locked, the delay through the delay chain is equivalent to one reference clock cycle, and the delay setting is sent out to the DQS delay block.