126.96.36.199. Regional Clock Networks
RCLK networks provide low clock insertion delay and skew for logic contained within a single RCLK region. The Intel® Arria® 10 IOEs and internal logic within a given region can also drive RCLKs to create internally-generated regional clocks and other high fan-out signals.
Intel® Arria® 10 devices provide RCLKs that can drive through the chip horizontally. RCLKs cover all the SCLK spine regions in the same row of the device. The top and bottom HSSI and I/O banks have RCLKs that cover 2 rows vertically. The other intermediate HSSI and I/O banks have RCLKs that cover 6 rows vertically. The following figure shows the RCLK network coverage.
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