Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents Regional Clock Networks

RCLK networks provide low clock insertion delay and skew for logic contained within a single RCLK region. The Intel® Arria® 10 IOEs and internal logic within a given region can also drive RCLKs to create internally-generated regional clocks and other high fan-out signals.

Intel® Arria® 10 devices provide RCLKs that can drive through the chip horizontally. RCLKs cover all the SCLK spine regions in the same row of the device. The top and bottom HSSI and I/O banks have RCLKs that cover 2 rows vertically. The other intermediate HSSI and I/O banks have RCLKs that cover 6 rows vertically. The following figure shows the RCLK network coverage.

Figure 54. RCLK Networks in Intel® Arria® 10 Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.