Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

7.3.3.6. User Mode

You can enable the optional INIT_DONE pin to monitor the initialization stage. After the INIT_DONE pin is pulled high, initialization completes and your design starts executing. The user I/O pins then function as specified by your design.

During device initialization stage, the FPGA registers, core logic, and I/O are not released from reset at the same time. The increase in clock frequency, device size, and design complexity require a reset strategy that considers the differences in the release from reset. Intel® recommends that you use the following implementations to reset your design properly and until the device has fully entered user mode:

  • Hold the entire design in reset for a period of time by following the CONF_DONE high to user mode (tCD2UM) or CONF_DONE high to user mode with CLKUSR option turned on (tCD2UMC) specifications as defined in the Intel® Arria® 10 Device Datasheet before starting any operation after the device enters into user mode. For example, the tCD2UM range for Intel® Arria® 10 device is between 175 us to 830 us.
  • Use an internal init_done signal to hold the reset of your core registers, core logic, and I/O registers until the device has fully entered user mode. The internal init_done signal is high (enabled) until the entire device enters user mode.
    
    twentynm_controller u1 (
    
    .initdonecore(init_done)
    
    );
  • If you have an external device that reacts based on an Intel® FPGA output pin, perform the following steps to avoid false reaction:
    • Ensure that the external device ignores the state of the FPGA output pin until the external INIT_DONE pin goes high. Refer to the tCD2UM or tCD2UMC specifications in the Intel® Arria® 10 Device Datasheet for more information.
    • Keep the input state to the external device constant by using the external logic until the external INIT_DONE pin goes high.

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