4.1.2. Hierarchical Clock Networks
Intel® Arria® 10 devices cover 3 levels of clock networks hierarchy. The sequence of the hierarchy is as follows:
- GCLK, RCLK, PCLK, and GCLK and RCLK feedback clocks
- Section clock (SCLK)
- Row clocks
Each HSSI and I/O column contains clock drivers to drive down shared buses to the respective GCLK, RCLK, and PCLK clock networks.
Intel® Arria® 10 clock networks (GCLK, RCLK, and PCLK) are routed through SCLK before each clock is connected to the clock routing for each HSSI or I/O bank. The settings for SCLK are transparent. The Intel® Quartus® Prime software automatically routes the SCLK based on the GCLK, RCLK, and PCLK networks.
Each SCLK spine has a consistent height, matching that of HSSI and I/O banks. The number of SCLK spine in a device depends on the number of HSSI and I/O banks.
Intel® Arria® 10 devices provide a maximum of 33 SCLK networks in the SCLK spine region. The SCLK networks can drive six row clocks in each row clock region. The row clocks are the clock resources to the core functional blocks, PLLs, and I/O interfaces, and HSSI interfaces of the device. Six unique signals can be routed into each row clock region. The connectivity pattern of the multiplexers that drive each SCLK limits the clock sources to the SCLK spine region. Each SCLK can select the clock resources from GCLK, RCLK, LPCLK, or SPCLK lines.
The following figure shows SCLKs driven by the GCLK, RCLK, PCLK, or GCLK and RCLK feedback clock networks in each SCLK spine region. The GCLK, RCLK, PCLK, and GCLK and RCLK feedback clocks share the same SCLK routing resources. To ensure successful design fitting in the Intel® Quartus® Prime software, the total number of clock resources must not exceed the SCLK limits in each SCLK spine region.
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