Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 5/27/2022
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3.4.1.1. Two Sets of Delay Registers for Fixed-Point Arithmetic

The two delay registers along with the input cascade chain that can be used in fixed-point arithmetic 18 x 19 mode are the top delay registers and bottom delay registers. Delay registers are not supported in 18 × 19 multiplication summed with 36-bit input mode and 27 × 27 mode.

Figure 28. Input Register of a Variable Precision DSP Block in Fixed-Point Arithmetic 18 x 19 Mode for Intel® Arria® 10 DevicesThe figures show the data registers only. Registers for the control signals are not shown.


Figure 29. Input Register of a Variable Precision DSP Block in Fixed-Point Arithmetic 27 x 27 Mode for Intel® Arria® 10 DevicesThe figures show the data registers only. Registers for the control signals are not shown.


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