Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

9.7. JTAG Boundary-Scan Testing in Intel® Arria® 10 Devices Revision History

Date Version Changes
March 2017 2017.03.15 Rebranded as Intel.
May 2016 2016.05.02
  • Updated IDCODE.
  • Added note about SAMPLE instruction is not available for HSSI pins.
December 2015.12.14
  • Updated User I/O BSC with IEEE Std. 1149.1 BST Circuitry for Arria 10 Devices figure.
  • Added SHIFT_EDERROR_REG in Supported JTAG instruction table.
November 2015 2015.11.02 Added note to state that JTAG BST can be performed after nSTATUS and nCONFIG are high.
August 2014 2014.08.18
  • Updated the JTAG Private Instruction section to add a new instruction code.
  • Updated the I/O Voltage for JTAG Operation section to update the TDO output buffer details.
  • Updated the Performing BST section to add a note on performing BST in user mode.
  • Updated the Boundary-Scan Cells of an Arria 10 Device I/O Pin section.
December 2013 2013.12.02 Initial release.

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