Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents

6.1. Key Features of the Arria® 10 External Memory Interface Solution

  • The solution offers completely hardened external memory interfaces for several protocols.
  • The devices feature columns of I/Os that are mixed within the core logic fabric instead of I/O banks on the device periphery.
  • A single hard Nios® II block calibrates all the memory interfaces in an I/O column.
  • The I/O columns are composed of groups of I/O modules called I/O banks.
  • Each I/O bank contains a dedicated integer PLL (IO_PLL), hard memory controller, and delay-locked loop.
  • The PHY clock tree is shorter compared to previous generation Arria® devices and only spans one I/O bank.
  • Interfaces spanning multiple I/O banks require multiple PLLs using a balanced reference clock network.