184.108.40.206. GCLK Control Block
You can select the clock source for the GCLK select block either statically or dynamically using internal logic to drive the multiplexer-select inputs.
When selecting the clock source dynamically, you can select either PLL outputs (such as C0 or C1), or a combination of clock pins or PLL outputs.
You can set the input clock sources and the clkena signals for the GCLK network multiplexers through the Intel® Quartus® Prime software using the ALTCLKCTRL IP core.
When selecting the clock source dynamically using the ALTCLKCTRL IP core, choose the inputs using the CLKSELECT[0..1] signal.