Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

4.1.5.2. GCLK Control Block

You can select the clock source for the GCLK select block either statically or dynamically using internal logic to drive the multiplexer-select inputs.

When selecting the clock source dynamically, you can select either PLL outputs (such as C0 or C1), or a combination of clock pins or PLL outputs.

Figure 57. GCLK Control Block for Intel® Arria® 10 Devices


You can set the input clock sources and the clkena signals for the GCLK network multiplexers through the Intel® Quartus® Prime software using the ALTCLKCTRL IP core.

When selecting the clock source dynamically using the ALTCLKCTRL IP core, choose the inputs using the CLKSELECT[0..1] signal.

Note: You can only switch dedicated clock inputs from the same I/O or HSSI bank.

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