Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents Hard Memory Controller

The Arria® 10 hard memory controller is designed for high speed, high performance, high flexibility, and area efficiency. The hard memory controller supports all the popular and emerging memory standards including DDR4, DDR3, and LPDDR3.

The high performance is achieved by implementing advanced dynamic command and data reordering algorithms. In addition, efficient pipelining techniques are also applied to the design to improve the memory bandwidth usage and reduce the latency while keeping the speed high. The hard solution offers the best availability and shorter time-to-market. The timing inside the controller and from the controller to the PHY have been pre-closed by Intel—simplifying timing closure.

The controller architecture is a modular design and fits in a single I/O bank. This structure offers you the best flexibility from the hard solution:

  • You can configure each I/O bank as either one of the following paths:
    • A control path that drives all the address/command pins for the memory interface.
    • A data path that drives up to 32 data pins for DDR-type interfaces.
  • You can place your memory controller in any location.
  • You can pack up multiple banks together to form memory interfaces of different widths up to 144 bits.

For more flexibility, you can bypass the hard memory controller and use your custom IP if required.

Figure 127. Hard Memory Controller Architecture

The hard memory controller consists of the following logic blocks:

  • Core and PHY interfaces
  • Main control path
  • Data buffer controller
  • Read and write data buffers

The core interface supports the Avalon® Memory-Mapped (Avalon-MM) interface protocol. The interface communicating to the PHY follows the Altera PHY Interface (AFI) protocol. The whole control path is split into the main control path and the data buffer controller.