Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents Clock Tree

The Arria® 10 external memory interface PHY clock network is designed to support the 1.2 GHz DDR4 memory standard.

Compared to previous generation devices, the PHY clock network has a shorter clock tree that generates less jitter and less duty cycle distortion.

The PHY clock network consists of these clock trees:

  • Reference clock tree
  • PHY clock tree
  • DQS clock tree
Figure 129. Clock Network DiagramThe reference clock tree adopts a modular design to facilitate easy integration.