184.108.40.206.3. Utilized FIT
The Projected SEU FIT by Component report's Utilized CRAM FIT represents provable deflation of the FIT rate to account for CRAM upsets that do not matter to the design. Thus, the SEU incidence is always higher than the utilized FIT rate.
Comparing .smh Critical Bits Report to Utilized Bit Count
The number of design critical bits that the Compiler reports during .smh generation correlates to the utilized bits in the report, but it is not the same value. The difference occurs because the .smh file includes all bits in a resource, even when the resource usage is partial.
Considerations for Small Designs
The raw FIT for the entire device is always correct. In contrast, the utilized FIT is very conservative, and only becomes accurate for designs that reasonably fill up the chosen device. FPGAs contain overhead, such as the configuration state machine, the clock network control logic, and the I/O calibration block. These infrastructure blocks contain flip flops, memories, and sometimes I/O configuration blocks.
The Projected SEU FIT by Component report includes the constant overhead for GPIO and HSSI calibration circuitry for first I/O block or transceiver the design uses. Because of this overhead, the FIT of a 1-transceiver design is much higher than 1/10 the FIT of a 10-transceiver design. However, a trivial design such as “a single AND gate plus flipflop” could use so few bits that its CRAM FIT rate is 0.01, which the report rounds to zero.