10.4.2.1.3. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is Equal to 2'b11
The following timing diagram shows the IP core timing to access the voltage sensor when MD[1:0] is equal to 2'b11.
- A low-to-high transition on the corectl signal enables the core access mode.
Wait for a minimum of two clock cycles before proceeding to step 2.
- De-asserting the reset signal releases the voltage sensor from the reset state.
Wait for a minimum two clock cycles before proceeding to step 3.
- Configure the voltage sensor by writing the configuration registers and asserting the coreconfig signal for eight clock cycles. The configuration register access mode is 8 bits and configuration data is shifted in serially.
- Specify the channel for conversion on the chsel[3:0] signal. Data on the chsel[3:0] signal must be stable before the coreconfig signal is de-asserted.
- The coreconfig signal going low indicates the start of the conversion based on the configuration defined in the configuration register and the chsel[3:0] signal.
- Specify the next channel for conversion on the chsel[3:0] signal. Data on the chsel[3:0] signal must be stable one cycle before the eoc signal asserts. Poll the eoc and eos status signals to check if conversion for the first channel defined by the chsel[3:0] signal in step 4 is complete. Latch the output data on the dataout[5:0] signal at the falling edge of the eoc signal.
- Repeat step 6 for all the subsequent channels.
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