Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 5/27/2022
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6.8. External Memory Interface in Intel® Arria® 10 Devices Revision History

Date Version Changes
December 2017 2017.12.15
  • Updated Delay-Locked Loop frequency range to 600MHz - 1.3GHz.
  • Updated maximum burst length for burst adaptor in Table 90 table.
June 2017 2017.06.21 Updated the note about the memory interfaces support to clarify that I/O banks with less than 48 pins can be used for data pins only. Therefore, all external memory interfaces require at least one 48-pins I/O bank to place the A/C pins.
March 2017 2017.03.15
  • Removed Avalon Streaming (Avalon ST) interface protocol support for hard memory controller.
  • Rebranded as Intel.
October 2016 2016.10.31

Removed the F36 package from the Intel® Arria® 10 GX device family variant.

May 2016 2016.05.02
  • Updated maximum frequency for QDR II, QDR II+ and QDR II+ Xtreme SRAM.
  • Updated maximum supported frequency for DDR4 SDRAM.
  • Removed NF40 and UF45 packages support for Arria 10 GT devices.
  • Added Guideline: Usage of I/O Bank 2A for External Memory Interfaces section in External Memory Interface I/O Pins in Intel® Arria® 10 Devices chapter.
  • Removed LPDDR3 support in HPS Hard Memory Controller.
  • Added HPS External Memory Interface Connections in Intel® Arria® 10 chapter to explain the restriction for using HPS EMIF with non-HPS EMIF within the same the device.
  • Updated number of interfaces supported for DDR4 x40 with ECC in F36 and KF40 packages (GX 570 and GX 660 devices).
  • Removed note and footnote about using 3 V I/O bank to support DDR4 x40 with ECC interfaces.
  • Added tables to show numbers of supported memory interfaces for Intel® Arria® 10 SX device packages when HPS EMIF instances are used within the same device.
  • Removed burst chop feature for DDR3 and DDR4 in Table Main Control Path Components.
  • Removed DDR4 gear down mode feature in Table Hard Memory Controller Features.
  • Removed DQS tracking feature in Hard Memory Controller in Table Hard Memory Controller Features.
November 2015 2015.11.02
  • Removed BC4 and On-the-fly supports for DDR4, DDR3 and DDR3L SDRAM in Table Types of Altera IP Support for Each Memory Standard.
  • Change supported DQ Group for DDR4, DDR3, and DDR3L SDRAM to x4/x8 in Table Types of Altera IP Support for Each Memory Standard.
  • Added LPDDR3 SDRAM in hard memory controller and IP support.
  • Added link to Arria 10 Device Datasheet - Memory Standards Supported by the Hard Memory Controller and Arria 10 Device Datasheet - Memory Standards Supported by the Soft Memory Controller.
  • Added Intel® Arria® 10 package support for DDR3 x32 with ECC for HPS, DDR3 x 72 Single and Dual-Rank for HPS, DDR4 x32 with ECC for HPS, and DDR3 x72 Single-Rank tables.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.15 Removed the DFI label on the figure showing the hard memory controller architecture. Intel® Arria® 10 devices do not support DFI.
May 2015 2015.05.15 Corrected the DDR3 half rate and quarter rate maximum frequencies in the table that lists the memory standards supported by the Intel® Arria® 10 hard memory controller.
May 2015 2015.05.04 Updated the table that lists the memory standards supported by the hard memory controller in Intel® Arria® 10 devices.
January 2015 2015.01.23
  • Updated the table that lists the memory standards supported by Intel® Arria® 10 devices.
  • Removed hard memory controller and IP support for LPDDR3 SDRAM.
  • Removed support for RLDRAM 2.
  • Updated support for QDR II+/II+ Xtreme SRAM to also include QDR II SRAM.
  • Added soft memory controller support for QDR IV.
  • Added footnote to clarify that the number of DDR4 x32 interfaces support for the F34 package of the Intel® Arria® 10 SX 480 device includes using I/O bank 2K. If you use I/O bank 2K in a DDR4 x32 interface for the FPGA, the HPS will not have access to a DDR4 x32 interface.
  • Added information to clarify that the DDR3 and DDR4 x32 interface with ECC includes 32 bits data and 8 bits ECC.
  • Removed information about hard and soft portions of the Nios subsytem. The hard memory controller IP for Intel® Arria® 10 calibrates the external memory interface using the hard Nios II processor only.
August 2014 2014.08.18
  • Removed hard memory controller half rate support for DDR4 SDRAM.
  • Removed hard memory controller and IP support for DDR3U SDRAM.
  • Added soft memory controller full rate support for QDR II+ SRAM and QDR II+ Xtreme SRAM.
  • Updated the list of external memory standards supported by the HPS.
  • Updated the number of DDR3 x72 (single-rank) memory interfaces supported for the U19 package.
  • Removed the note about using 3 V I/O banks for the HPS. For the HPS, the 3 V I/O bank is not used for external memory interfaces.
  • Updated the number of DDR3 x72 (dual-rank) memory interfaces supported for the Arria 10 SX devices.
  • Updated the number of DDR4 x32 (with ECC) memory interfaces supported for the NF45 package of the Arria 10 GT 1150 device.
  • Added soft memory controller IP support for QDR II+ SRAM.
  • Added information to clarify that RLDRAM3 support uses hard PHY with soft memory controller.
  • Updated the table that lists the features of the hard memory controller to improve accuracy and add missing information.
  • Added a note before the topics listing external memory interface package support to clarify that not all I/O banks are available for external memory interfaces.
  • Moved the external memory interface pins guidelines and the examples of external memory interface implementations for DDR4 to the External Memory Interface Handbook.
December 2013 2013.12.10 Updated the HPS memory standards support from LPDDR2 to LPDDR3.
December 2013 2013.12.02 Initial release.

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