Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 1/18/2023
Document Table of Contents Global Clock Networks

GCLK networks serve as low-skew clock sources for functional blocks, such as adaptive logic modules (ALMs), digital signal processing (DSP), embedded memory, and PLLs. Intel® Arria® 10 I/O elements (IOEs) and internal logic can also drive GCLKs to create internally-generated global clocks and other high fan-out control signals, such as synchronous or asynchronous clear and clock enable signals.

Intel® Arria® 10 devices provide GCLKs that can drive throughout the device. GCLKs cover every SCLK spine region in the device. Each GCLK is accessible through the direction as indicated in the Symbolic GCLK Networks diagram.

Figure 53. Symbolic GCLK Networks in Intel® Arria® 10 Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

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