Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents
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7.1. Enhanced Configuration and Configuration via Protocol

Table 93.  Configuration Schemes and Features of Intel® Arria® 10 Devices Intel® Arria® 10 devices support 1.8 V programming voltage and several configuration schemes.
Scheme Data Width

Max Clock Rate


Max Data Rate


Decompression Design Security 29 Partial Reconfiguration 30 Remote System Update
JTAG 1 bit 33 33 Yes 31
Active Serial (AS) through the EPCQ-L configuration device

1 bit,

4 bits

100 400 Yes Yes Yes 31 Yes
Passive serial (PS) through CPLD or external microcontroller 1 bit 100 100 Yes Yes Yes 31 Parallel Flash Loader (PFL) Intel® FPGA IP core
Fast passive parallel (FPP) through CPLD or external microcontroller 8 bits 100 3200 Yes Yes Yes 32 PFL Intel® FPGA IP core
16 bits Yes Yes
32 bits Yes Yes
Configuration via HPS 16 bits 100 3200 Yes Yes Yes 32
32 bits Yes Yes
Configuration via Protocol [CvP (PCIe*)]

x1, x2, x4, x8 lanes

8000 Yes Yes Yes 31

You can configure Intel® Arria® 10 devices through PCIe using Configuration via Protocol (CvP). The Intel® Arria® 10 CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.

28 Enabling either compression or design security features affects the maximum data rate. Refer to the Intel® Arria® 10 Device Datasheet for more information.
29 Encryption and compression cannot be used simultaneously.
30 Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial reconfiguration, contact Intel® for support.
31 Partial configuration can be performed only when it is configured as internal host.
32 Supported at a maximum clock rate of 100 MHz.