Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 5/27/2022
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4.3. Clock Networks and PLLs in Intel® Arria® 10 Devices Revision History

Document Version Changes
2019.06.24
  • Updated the description for single-ended clock inputs in the Dedicated Clock Input Pins section.
  • Added description about PLL lock range in the Reference Clock Sources section.
Date Version Changes
December 2017 2017.12.15
  • Updated the notes on PLL reset in the Reset section.
  • Updated the description on I/O-PLL-to-I/O-PLL cascading in the PLL Cascading section.
  • Added KDB link on PLL jitter compensation in the following sections:
    • PLL Cascading
    • Reference Clock Sources
  • Updated the links in the PLL Reconfiguration and Dynamic Phase Shift section.
May 2017 2017.05.08
  • Updated information on PLL cascading.
  • Removed all "Preliminary" marks.
March 2017 2017.03.15 Rebranded as Intel.
October 2016 2016.10.31
  • Changed clock switchover control signal from clkswitch to extswitch.
  • Updated the clock switchover control signal to active low in the Manual Clock Switchover section.
May 2016 2016.05.02
  • Updated the Clock Resources in Intel® Arria® 10 Devices table.
    • Updated the number of resources available for HSSI.
    • Removed fPLL M counter output as the source of clock resource for HSSI.
  • Updated descriptions on dedicated clock input pins.
  • Updated the note in Clock Power Down section.
  • Updated the description on fPLL mode in Intel® Arria® 10 PLLs section.
  • Updated Fractional PLL High-Level Block Diagram for Intel® Arria® 10 diagram.
  • Removed dedicated refclk input in I/O PLL High-Level Block Diagram for Intel® Arria® 10 Devices diagram.
  • Updated supported PLL cascading mode for Intel® Arria® 10 devices.
  • Added Reference Clock Sources section.
November 2015 2015.11.02
  • Updated the description in Hierarchical Clock Networks section: Intel® Arria® 10 devices provide a maximum of 33 SCLK networks in the SCLK spine region.
  • Updated GCLK Control Block for Intel® Arria® 10 Devices diagram.
  • Removed the following description in the GCLK Control Block section: The inputs from the clock pins feed the inclk[0..1] ports of the multiplexer, and the PLL outputs feed the inclk[2..3] ports.
  • Added descriptions about I/O PLL in the Intel® Arria® 10 PLLs section.
  • Updated PLL Features in Intel® Arria® 10 Devices table.
    • Updated the feature from integer and fractional PLLs to integer and fractional modes.
    • Updated M counter divide factors for fPLL from "1 to 320" to "8 to 127".
    • Updated M counter divide factors for I/O PLL from "1 to 512" to "4 to 160".
    • Updated N counter divide factors for fPLL from "1 to 512" to "1 to 80".
    • Updated C counter divide factors for fPLL from "1 to 320" to "1 to 512".
    • Removed normal compensation support in fPLL.
    • Changed "Fractional PLL bonding compensation" to "Feedback compensation bonding".
    • Updated phase shift resolution for fPLL from 41.667 ps to 72 ps.
  • Updated compensation mode in Fractional PLL High-Level Block Diagram for Intel® Arria® 10 Devices.
  • Updated clock feedback modes for fPLL.
    • Removed normal compensation.
    • Changed fPLL bonding compensation to feedback compensation bonding.
  • Updated description for dynamic phase shift in the PLL Reconfiguration and Dynamic Phase Shift section.
  • Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.04
  • Updated the number of RCLK/RCLK feedback from 12 to 8 in the Hierarchical Clock Networks in SCLK Spine diagram.
  • Added description to the Global Clock Networks section: Each GCLK is accessible through the direction as indicated in the Symbolic GCLK Networks diagram.
  • Updated HSSI outputs to HSSI clock outputs in the Clock Network Sources section.
  • Specified that the fPLL and I/O PLL clock outputs can drive all clock networks in the PLL Clock Outputs section.
  • Added descriptions on PLL cascading bandwidth requirements and PLL cascading modes.
  • Added a note on fPLL reset requirement in the PLL Control Signals (Reset) section.
January 2015 2015.01.23
  • Updated the dedicated clock input pins that have dedicated connections to the I/O PLL (CLK_[2,3][A..L]_[0,1][p,n]) when used as single-ended clock inputs.
  • Removed the dedicated clock input pins, CLK_[2,3][A..L]_[0,1]n , that drive the I/O PLLs over global or regional clock networks and do not have dedicated routing paths to the I/O PLLs.
  • Removed a note to Internal Logic in the Clock Network Sources section. Note removed: Internally-generated GCLKs or RCLKs cannot drive the Intel® Arria® 10 PLLs. The input clock to the PLL has to come from dedicated clock input pins, PLL-fed GCLKs, or PLL-fed RCLKs.
  • Added clock control block pin mapping tables for HSSI and I/O columns.
  • Updated Fractional PLL High-Level Block Diagram for Intel® Arria® 10 Devices. Changed CLKp to REFCLK_GXBp and CLKn to REFCLK_GXBn in the note for dedicated clock inputs.
  • Updated the note to dedicated clock inputs in I/O PLL High-Level Block Diagram for Intel® Arria® 10 Devices because all four clock inputs can be used as dedicated clock inputs for I/O PLL. The note was changed from "For single-ended clock inputs, only the CLKp pin has a dedicated connection to the PLL. If you use the CLKn pin, a global or regional clock is used." to "For single-ended clock inputs, both the CLKp and CLKn pins have dedicated connection to the PLL."
  • Added PLL cascading information.
  • Clarified that when the reset signal is driven low again, the PLL resynchronizes to its input clock source as it re-locks.
  • Added description for clock feedback mode: Clock feedback modes compensate for clock network delays to align the PLL clock input rising edge with the rising edge of the clock output. Select the appropriate type of compensation for the timing critical clock path in your design. PLL compensation is not always needed. A PLL should be configured in direct (no compensation) mode unless a need for compensation is identified. Direct mode provides the best PLL jitter performance and avoids expending compensation clocking resources unnecessarily.
  • Updated clock switchover clkswitch signal from positive trigger to negative trigger.
  • Added the links to the following documents:
    • Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide—Provides more information about I/O PLL software support in the Intel® Quartus® Prime software.
    • PLLs and Clock Networks chapter, Intel® Arria® 10 Transceiver PHY User Guide—Provides more information about fPLL software support in the Intel® Quartus® Prime software.
    • I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 Devices—Provides more information about implementing I/O PLL reconfiguration in Altera PLL Reconfig IP core and implementing I/O PLL dynamic phase shift in Altera IOPLL IP core.
August 2014 2014.08.18
  • Updated the dedicated clock input pins name from HSSI banks.
  • Updated the description in Hierarchical Clock Networks section.
  • Updated the description in Dedicated Clock Input Pins section.
  • Removed PCLK network from the Internal Logic section.
  • Updated the description in PCLK Control Block section.
  • Updated the following diagrams:
    • PCLK Control Block for HSSI Column for Arria 10 Devices
    • PCLK Control Block for I/O Column for Arria 10 Devices
  • Removed IQTXRXCLK compensation mode.
  • Updated fractional PLL and I/O PLL high-level block diagrams.
  • Updated the description for manual clock switchover.
  • Updated the description for PLL reconfiguration.
December 2013 2013.12.02 Initial release.

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