Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 5/27/2022
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2.3. Embedded Memory Features

Table 5.  Memory Features in Intel® Arria® 10 Devices This table summarizes the features supported by the embedded memory blocks.
Features M20K MLAB
Maximum operating frequency

730 MHz

700 MHz

Total RAM bits (including parity bits)

20,480

640

Parity bits Supported
Byte enable Supported Supported
Packed mode Supported
Address clock enable Supported
Simple dual-port mixed width Supported
True dual-port mixed width Supported
FIFO buffer mixed width Supported
Memory Initialization File (.mif) Supported Supported
Mixed-clock mode Supported Supported
Fully synchronous memory Supported Supported
Asynchronous memory Only for flow-through read memory operations.
Power-up state

Output ports are cleared.

  • Registered output ports—Cleared.
  • Unregistered output ports—Read memory contents.
Asynchronous clears Output registers and output latches Output registers and output latches
Write/read operation triggering Rising clock edges Rising clock edges
Same-port read-during-write

Output ports set to "new data" or "don't care".

Output ports set to "don't care".

Mixed-port read-during-write Output ports set to "old data" or "don't care". Output ports set to "old data", "new data", "don't care", or "constrained don't care".
ECC support

Soft IP support using the Intel® Quartus® Prime software.

Built-in support in x32-wide simple dual-port mode.

Soft IP support using the Intel® Quartus® Prime software.

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