Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

7.2.1.5.2. Trace Length Guideline

The maximum trace length apply to both single- and multi-device AS configuration setups as listed in the following table. The trace length is the length from the Intel® Arria® 10 device to the EPCQ-L device.

Note: To evaluate the data setup (tSU) and data hold time (tDH) slack on your board in order to ensure that you are meeting the tSU and tDH requirements, Intel® recommends that you follow the guideline in the Evaluating Data Setup and Hold Timing Slack section of the AN822: Intel FPGA Configuration Device Migration Guideline.
Table 93.  Maximum Trace Length for AS x1 and x4 Configurations for Intel® Arria® 10 Devices
Intel® Arria® 10 Device AS Pins Maximum Board Trace Length (Inches)
12.5/ 25/ 50 MHz 100 MHz
DCLK 10 6
AS_DATA[3..0] 10 6
nCSO[2..0] 10 6

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