Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents

7.2.4. JTAG Configuration

In Arria® 10 devices, JTAG instructions take precedence over other configuration schemes.

The Quartus® Prime software generates an SRAM Object File (.sof) that you can use for JTAG configuration using a download cable in the Quartus® Prime software programmer. Alternatively, you can use the JRunner software with .rbf or a JAM™ Standard Test and Programming Language (STAPL) Format File (.jam) or JAM Byte Code File (.jbc) with other third-party programmer tools.

Note: You cannot use the Arria® 10 decompression or design security features if you are configuring your Arria® 10 device using JTAG-based configuration.

The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on Arria® 10 devices do not affect JTAG boundary-scan or programming operations.

The Intel FPGA download cable can support VCCPGM supply at 1.5 V or 1.8 V; it does not support a target supply voltage of 1.2 V.