Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

1.4. Logic Array Blocks and Adaptive Logic Modules in Intel® Arria® 10 Devices Revision History

Document Version Changes
2019.12.30 Updated the following signal names in ALM Connection Details for Intel® Arria® 10 Devices figure:
  • aclr[1:0] to labclr[1:0]
  • sclr to synclr
  • clk[2:0] to labclk[2:0]
Date Version Changes
March 2017 2017.03.15 Rebranded as Intel.
October 2016 2016.10.31 Added description on clock source in the LAB Control Signals section.
November 2015 2015.11.02 Changed instances of Quartus II to Quartus Prime.
December 2013 2013.12.02 Initial release.

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