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1. Logic Array Blocks and Adaptive Logic Modules in Arria® 10 Devices
2. Embedded Memory Blocks in Arria® 10 Devices
3. Variable Precision DSP Blocks in Arria® 10 Devices
4. Clock Networks and PLLs in Arria® 10 Devices
5. I/O and High Speed I/O in Arria® 10 Devices
6. External Memory Interfaces in Arria® 10 Devices
7. Configuration, Design Security, and Remote System Upgrades in Arria® 10 Devices
8. SEU Mitigation for Arria® 10 Devices
9. JTAG Boundary-Scan Testing in Arria® 10 Devices
10. Power Management in Arria® 10 Devices
2.1. Types of Embedded Memory
2.2. Embedded Memory Design Guidelines for Arria® 10 Devices
2.3. Embedded Memory Features
2.4. Embedded Memory Modes
2.5. Embedded Memory Clocking Modes
2.6. Parity Bit in Embedded Memory Blocks
2.7. Byte Enable in Embedded Memory Blocks
2.8. Memory Blocks Packed Mode Support
2.9. Memory Blocks Address Clock Enable Support
2.10. Memory Blocks Asynchronous Clear
2.11. Memory Blocks Error Correction Code Support
2.12. Embedded Memory Blocks in Arria® 10 Devices Revision History
3.4.1. Input Register Bank
3.4.2. Pipeline Register
3.4.3. Pre-Adder for Fixed-Point Arithmetic
3.4.4. Internal Coefficient for Fixed-Point Arithmetic
3.4.5. Multipliers
3.4.6. Adder
3.4.7. Accumulator and Chainout Adder for Fixed-Point Arithmetic
3.4.8. Systolic Registers for Fixed-Point Arithmetic
3.4.9. Double Accumulation Register for Fixed-Point Arithmetic
3.4.10. Output Register Bank
4.2.1. PLL Usage
4.2.2. PLL Architecture
4.2.3. PLL Control Signals
4.2.4. Clock Feedback Modes
4.2.5. Clock Multiplication and Division
4.2.6. Programmable Phase Shift
4.2.7. Programmable Duty Cycle
4.2.8. PLL Cascading
4.2.9. Reference Clock Sources
4.2.10. Clock Switchover
4.2.11. PLL Reconfiguration and Dynamic Phase Shift
5.1. I/O and Differential I/O Buffers in Arria® 10 Devices
5.2. I/O Standards and Voltage Levels in Arria® 10 Devices
5.3. Altera FPGA I/O IP Cores for Arria® 10 Devices
5.4. I/O Resources in Arria® 10 Devices
5.5. Architecture and General Features of I/Os in Arria® 10 Devices
5.6. High Speed Source-Synchronous SERDES and DPA in Arria® 10 Devices
5.7. Using the I/Os and High Speed I/Os in Arria® 10 Devices
5.8. I/O and High Speed I/O in Arria® 10 Devices Revision History
5.6.1. Arria® 10 LVDS SERDES Usage Modes
5.6.2. SERDES Circuitry
5.6.3. SERDES I/O Standards Support in Arria® 10 Devices
5.6.4. Differential Transmitter in Arria® 10 Devices
5.6.5. Differential Receiver in Arria® 10 Devices
5.6.6. PLLs and Clocking for Arria® 10 Devices
5.6.7. Timing and Optimization for Arria® 10 Devices
5.6.6.1. Clocking Differential Transmitters
5.6.6.2. Clocking Differential Receivers
5.6.6.3. Guideline: LVDS Reference Clock Source
5.6.6.4. Guideline: Use PLLs in Integer PLL Mode for LVDS
5.6.6.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
5.6.6.6. Guideline: Pin Placement for Differential Channels
5.6.6.7. LVDS Interface with External PLL Mode
5.7.1. I/O and High-Speed I/O General Guidelines for Arria® 10 Devices
5.7.2. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards
5.7.3. Guideline: Maximum Current Driving I/O Pins While Turned Off and During Power Sequencing
5.7.4. Guideline: Using the I/O Pins in HPS Shared I/O Banks
5.7.5. Guideline: Maximum DC Current Restrictions
5.7.6. Guideline: LVDS SERDES IP Core Instantiation
5.7.7. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
5.7.8. Guideline: Minimizing High Jitter Impact on Arria® 10 GPIO Performance
5.7.9. Guideline: Usage of I/O Bank 2A for External Memory Interfaces
6.1. Key Features of the Arria® 10 External Memory Interface Solution
6.2. Memory Standards Supported by Arria® 10 Devices
6.3. External Memory Interface Widths in Arria® 10 Devices
6.4. External Memory Interface I/O Pins in Arria® 10 Devices
6.5. Memory Interfaces Support in Arria® 10 Device Packages
6.6. External Memory Interface IP Support in Arria® 10 Devices
6.7. External Memory Interface Architecture of Arria® 10 Devices
6.8. External Memory Interface in Arria® 10 Devices Revision History
6.5.1. Arria® 10 Package Support for DDR3 x40 with ECC
6.5.2. Arria® 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank
6.5.3. Arria® 10 Package Support for DDR4 x40 with ECC
6.5.4. Arria® 10 Package Support for DDR4 x72 with ECC Single-Rank
6.5.5. Arria® 10 Package Support for DDR4 x72 with ECC Dual-Rank
6.5.6. HPS External Memory Interface Connections in Arria® 10
9.1. BST Operation Control
9.2. I/O Voltage for JTAG Operation
9.3. Performing BST
9.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry
9.5. Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
9.6. IEEE Std. 1149.1 Boundary-Scan Register
9.7. JTAG Boundary-Scan Testing in Arria® 10 Devices Revision History
10.1. Power Consumption
10.2. Power Reduction Techniques
10.3. Power Sense Line
10.4. Voltage Sensor
10.5. Temperature Sensing Diode
10.6. Power-On Reset Circuitry
10.7. Power Sequencing Considerations for Arria® 10 Devices
10.8. Power Supply Design
10.9. Power Management in Arria® 10 Devices Revision History
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9.1.2. Supported JTAG Instruction
JTAG Instruction | Instruction Code | Description |
---|---|---|
SAMPLE 42 / PRELOAD | 00 0000 0101 |
|
EXTEST | 00 0000 1111 |
|
BYPASS | 11 1111 1111 |
|
USERCODE | 00 0000 0111 | Selects the 32-bit USERCODE register and places it between the TDI and TDO pins to allow serial shifting of USERCODE out of TDO. |
IDCODE | 00 0000 0110 |
|
HIGHZ | 00 0000 1011 |
|
CLAMP | 00 0000 1010 |
|
PULSE_NCONFIG | 00 0000 0001 | Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is not affected. |
EXTEST_PULSE | 00 1000 1111 | Enables board-level connectivity checking between the transmitters and receivers that are AC coupled by generating three output transitions:
|
EXTEST_TRAIN | 00 0100 1111 | Behaves the same as the EXTEST_PULSE instruction except that the output continues to toggle on the TCK falling edge as long as the TAP controller is in the RUN_TEST/IDLE state. |
SHIFT_EDERROR_REG | 00 0001 0111 | The JTAG instruction connects the EMR to the JTAG pin in the error detection block between the TDI and TDO pins. |
Note: If the device is in a reset state and the nCONFIG or nSTATUS signal is low, the device IDCODE might not be read correctly. To read the device IDCODE correctly, you must issue the IDCODE JTAG instruction only when the nCONFIG and nSTATUS signals are high.
42 The SAMPLE JTAG instruction is not supported for high-speed serial interface (HSSI) pins.