Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

9.1.2. Supported JTAG Instruction

Table 117.  JTAG Instructions Supported by Intel® Arria® 10 Devices
JTAG Instruction Instruction Code Description
SAMPLE 42 / PRELOAD 00 0000 0101
  • Allows you to capture and examine a snapshot of signals at the device pins during normal device operation and permits an initial data pattern to be an output at the device pins.
  • Use this instruction to preload the test pattern into the update registers before loading the EXTEST instruction.
EXTEST 00 0000 1111
  • Allows you to test the external circuit and board-level interconnects by forcing a test pattern at the output pins, and capturing the test results at the input pins. Forcing known logic high and low levels on output pins allows you to detect opens and shorts at the pins of any device in the scan chain.
  • The high-impedance state of EXTEST is overridden by bus hold and weak pull-up resistor features.
BYPASS 11 1111 1111
  • Places the 1-bit bypass register between the TDI and TDO pins. During normal device operation, the 1-bit bypass register allows the BST data to pass synchronously through the selected devices to adjacent devices.
  • You will get a '0' reading in the bypass register out.
USERCODE 00 0000 0111 Selects the 32-bit USERCODE register and places it between the TDI and TDO pins to allow serial shifting of USERCODE out of TDO.
IDCODE 00 0000 0110
  • Identifies the devices in a JTAG chain. If you select IDCODE, the device identification register is loaded with the 32-bit vendor-defined identification code.
  • Selects the IDCODE register and places it between the TDI and TDO pins to allow serial shifting of IDCODE out of TDO.
  • IDCODE is the default instruction at power up and in the TAP RESET state. Without loading any instructions, you can go to the SHIFT_DR state and shift out the JTAG device ID.
HIGHZ 00 0000 1011
  • Sets all user I/O pins to an inactive drive state.
  • Places the 1-bit bypass register between the TDI and TDO pins. During normal operation, the 1-bit bypass register allows the BST data to pass synchronously through the selected devices to adjacent devices while tri-stating all I/O pins until a new JTAG instruction is executed.
  • If you are testing the device after configuration, the programmable weak pull-up resistor or the bus hold feature overrides the HIGHZ value at the pin.
CLAMP 00 0000 1010
  • Places the 1-bit bypass register between the TDI and TDO pins. During normal operation, the 1-bit bypass register allows the BST data to pass synchronously through the selected devices to adjacent devices while holding the I/O pins to a state defined by the data in the boundary-scan register.
  • If you are testing the device after configuration, the programmable weak pull-up resistor or the bus hold feature overrides the CLAMP value at the pin. The CLAMP value is the value stored in the update register of the boundary-scan cell (BSC).
PULSE_NCONFIG 00 0000 0001 Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is not affected.
EXTEST_PULSE 00 1000 1111 Enables board-level connectivity checking between the transmitters and receivers that are AC coupled by generating three output transitions:
  • Driver drives data on the falling edge of TCK in the UPDATE_IR/DR state.
  • Driver drives inverted data on the falling edge of TCK after entering the RUN_TEST/IDLE state.
  • Driver drives data on the falling edge of TCK after leaving the RUN_TEST/IDLE state.
EXTEST_TRAIN 00 0100 1111 Behaves the same as the EXTEST_PULSE instruction except that the output continues to toggle on the TCK falling edge as long as the TAP controller is in the RUN_TEST/IDLE state.
SHIFT_EDERROR_REG 00 0001 0111 The JTAG instruction connects the EMR to the JTAG pin in the error detection block between the TDI and TDO pins.
Note: If the device is in a reset state and the nCONFIG or nSTATUS signal is low, the device IDCODE might not be read correctly. To read the device IDCODE correctly, you must issue the IDCODE JTAG instruction only when the nCONFIG and nSTATUS signals are high.
42 The SAMPLE JTAG instruction is not supported for high-speed serial interface (HSSI) pins.

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