Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents
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5.7.8. Guideline: Minimizing High Jitter Impact on Intel® Arria® 10 GPIO Performance

In your Intel® Arria® 10 design flow, follow these guidelines to minimize undesired jitter impact on the GPIO performance.
  • Perform power delivery network analysis using Intel PDN tool 2.0. This analysis helps you to design a robust and efficient power delivery networks with the necessary decoupling capacitors. Use the Intel® Arria® 10 Early Power Estimator (EPE) to determine the current requirements for VCC and other power supplies. Perform the PDN analysis based on the current requirements of all the power supply rails especially the VCC power rail.
  • Use voltage regulator with remote sensor pins to compensate for the DC IR drop associated with the PCB and device package from the VCC power supply while maintaining the core performance. For more details about the connection guideline for the differential remote sensor pins for VCC power, refer to the pin connection guidelines.
  • The input clock jitter must comply with the Intel® Arria® 10 PLL input clock cycle-to-cycle jitter specification to produce low PLL output clock jitter. You must supply a clean clock source with jitter of less than 120 ps. For details about the recommended operating conditions, refer to the PLL specifications in the device datasheet.
  • Use dedicated PLL clock output pin to transmit clock signals for better jitter performance. The I/O PLL in each I/O bank supports two dedicated clock output pins. You can use the PLL dedicated clock output pin as a reference clock source for the FPGA. For optimum jitter performance, supply an external clean clock source. For details about the jitter specifications for the PLL dedicated clock output pin, refer to the device datasheet.
  • If the GPIO is operating at a frequency higher than 250 MHz, use terminated I/O standards. SSTL, HSTL, POD and HSUL I/O standards are terminated I/O standards. Intel recommends that you use the HSUL I/O standard for shorter trace or interconnect with a reference length of less than two inches.
  • Implement the GPIO or source synchronous I/O interface using the Altera PHYLite for Parallel Interfaces IP core. Intel recommends that you use the Altera PHYLite for Parallel Interfaces IP core if you cannot close the timing for the GPIO or source-synchronous I/O interface for data rates of more than 200 Mbps. For guidelines to migrate your design from the Altera GPIO IP core to the Altera PHYLite for Parallel Interfaces IP core, refer to the related information.
  • Use the small periphery clock (SPCLK) network. The SPCLK network is designed for high speed I/O interfaces and provides the smallest insertion delay. The following list ranks the clock insertion delays for the clock networks, from the largest to the smallest:
    • Global clock network (GCLK)
    • Regional clock network (RCLK)
    • Large periphery clock network (LPCLK)
    • SPCLK