1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines
The Altera PHYLite for Parallel Interfaces IP core (or Altera PHYLite IP core) enables your design to achieve better timing performance. Intel recommends that you use the Altera PHYLite IP core for general purpose I/O (GPIO) data rates higher than 200 Mbps to achieve optimal out signal.
Switching an Altera GPIO design to the Altera PHYLite IP core is very resource intensive.
- The Altera PHYLite IP core uses up the IOPLL, the phy_clk network, in the particular I/O bank.
- You may not be able to use the external memory interfaces and the Altera PHYLite IP core as normal memory protocols in this I/O bank unless they operate at the frequency multiplication of the Altera GPIO interface being switched.
- You also cannot use the Altera LVDS SERDES IP core in the same I/O bank with Altera PHYLite IP core.
Did you find the information on this page useful?