AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

ID 683231
Date 5/08/2017

1.4.2. Use Case 2: Driving Data from FPGA through GPIO to External Device

Example 2 describes the driving of data from FPGA through GPIO to an external device with a shared oscillator clock. This case uses the PLL output clock as a sampling clock to the user logic.

The oscillator clock goes into the FPGA GCLK network to drive the output data through GPIO to Off-chip. Off-chip clock uses the shared oscillator. The clock source of the other user logic comes from the PLL clock out.

You can use one of the two following methods to migrate the GPIO to Altera PHYLite IP core using the output clock from the IOPLL supplied to the user logic:

  1. Generate the output clock from the Altera PHYLite IP core's output clock.
    • The PHYLite IP core can export 4 additional IOPLL output clocks based on the specified configuration.
    • You can calculate the actual support clock frequency based on the formula:
      Output Clock Frequency = VCO Frequency/ c Counter
      • c Counter = Integers within 1–511
      • Voltage-controlled oscillator (VCO) frequency = (Memory/Interface clock frequency) × (VCO frequency multiplication factor)
        Note: Refer to the Altera PHYLite for Parallel Interfaces IP core parameter editor for more information.
    Figure 5. Generating Output Clock from PHYLite Output Clock
  2. Instantiate a new IOPLL in the adjacent I/O bank (where the PHYLite block resides), if the Altera PHYLite IOPLL output clocks do not support the desired output clock frequency.
    Figure 6. Instantiating a New I/O PLL