1.1.1. Parameter Settings
Follow the setting guidelines to instantiate a 1-bit single data rate (SDR) or double data rate (DDR) design.
| Parameter | Setting | Notes |
|---|---|---|
| Number of groups | 1 | – |
| General Tab | ||
| Interface clock frequency | Configure the frequency based on the required data rate. | The interface clock frequency is equal to data rate speed for SDR and half of the data rate speed for DDR. |
| Use core PLL reference clock connection | Turn on if your reference clock source is from the output of PLL or clock source from the core. | – |
| Use recommended PLL reference clock frequency | Turn on if the default frequency matches your reference clock frequency. Else, turn off the option and choose the desired reference clock frequency from the drop down list. |
– |
| Clock rate of user logic | Specify the clock frequency to full, half, or quarter, based on the core logic. | For example, if the data rate speed sent from the FPGA to the external device is toggling at 200 Mbps in DDR mode, a half rate interface means that the user logic in the FPGA runs at 100 MHz. |
| I/O standard | Specify the desired I/O standard. | – |
| Group 0 Tab
Note: In the Altera PHYLite IP core, the strobe_in and strobe_out ports are equivalent to the source synchronous clock interface to the input and output data.
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| Pin type | Specify based on the direction of the data pins. | – |
| Pin width | Specify the desired data width. | – |
| DDR/SDR | Specify the desired data rate mode. | – |
| Read Latency (When you configure the Altera PHYLite IP core as an input interface.) |
Specify the expected read latency. |
For example, a design with an external clock frequency of 100 MHz in full rate has a valid read latency of 3–63 external interface clock cycles. |
| Capture strobe phase shifty | Configure based on the desired phase shift of the input strobe relative to the input data. | For example in DDR mode, configure the phase shift to 90° would shift the edge-aligned input data/strobe to center-alignment at the read FIFO. |
| Write Latency (When you configure the Altera PHYLite IP core as an output interface.) |
Specify a value within 0–3 | Indicates the number of external interface clock cycles to delay the output data. |
| Use output strobe | Turn on if you want to enable the output strobe pin. | – |
| Output strobe phase | Specify based on the desired phase relationship between data and strobe being output from the IP core. | For example in DDR mode, configuring the phase shift to 90° would shift the strobe to center align with the output data |
| Data configuration | Specify the pin configuration of the data to be used as single ended or differential signaling. | – |
| Strobe configuration | Specify the type of strobe pin configuration to be used as single ended or differential signaling. | – |
| Use Default OCT Values | Turned on by default. | Turn off if you want to configure your desired input or output OCT values or you do not want any termination. |
| Generate Input/Output Delay Constraints for this group | Turned on by default. | Specifies the input/output delay setup or hold constraint against the input/output strobe of the group. |