AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

ID 683231
Date 5/08/2017

1.4.3. Use Case 3: Multiple-Speed Parallel Interfaces

Example 3 shows multiple-speed parallel interfaces with specific reference clock frequency.

To migrate the multi-speed parallel interface GPIO solution to Altera PHYLite, you must split the solution into two different I/O banks to run at different data rate.

Figure 7. Multiple-Speed Parallel Interfaces