AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

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ID 683231
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines x
1.1. Implementing the Altera PHYLite Design 1.2. Mapping the Interface Signals 1.3. Performance Comparison 1.4. Use Case Examples 1.5. Altera GPIO to Altera PHYLite Design Example 1.6. Document Revision History
1.1. Implementing the Altera PHYLite Design x
1.1.1. Parameter Settings
1.4. Use Case Examples x
1.4.1. Use Case 1: Source Synchronous I/O Interface 1.4.2. Use Case 2: Driving Data from FPGA through GPIO to External Device 1.4.3. Use Case 3: Multiple-Speed Parallel Interfaces 1.4.4. Use Case 4: GPIO Interface Using 3.0V/2.5V I/O Standard 1.4.5. Use Case 5: Generating Output Clock through GPIO Output Pin
1.5. Altera GPIO to Altera PHYLite Design Example x
1.5.1. Simulation Diagrams 1.5.2. Design Verification
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

1.6. Document Revision History

The following table lists the revision history for this document.
Table 6.  Document Revision History
Date Version Changes
May 2017 2017.05.08 Rebranded as Intel.
December 2016 2016.12.30 Edited the link to the design files.
December 2015 2015.12.14 Initial release.

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