AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines
ID
683231
Date
5/08/2017
Public
1.4.1. Use Case 1: Source Synchronous I/O Interface
1.4.2. Use Case 2: Driving Data from FPGA through GPIO to External Device
1.4.3. Use Case 3: Multiple-Speed Parallel Interfaces
1.4.4. Use Case 4: GPIO Interface Using 3.0V/2.5V I/O Standard
1.4.5. Use Case 5: Generating Output Clock through GPIO Output Pin
1.4. Use Case Examples
You use the use case examples as guidelines to migrate the Altera GPIO IP core application to the Altera PHYLite IP core.