AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

ID 683231
Date 5/08/2017

1.4.5. Use Case 5: Generating Output Clock through GPIO Output Pin

Example 5 describes the generation of an output clock through a GPIO output pin. The source of the output clock is from the transceiver SERDES recovered clock.
Figure 8. Recovered Clock from Transceiver Produced Through GPIO Interface

Generate the output clock through the PHYLite IP core if you use a regular I/O.

Figure 9. Recovered Clock Feeding Through I/O PLL to Generate Output Clock Using Dedicated Clock Out Pin

Figure 10. Recovered Clock Feeding Through Altera PHYLite IP Core to Generate Output Clock Using Regular GPIO Pin

Generating the recovered clock through a dedicated clock out pin from the IOPLL or through the Altera PHYLite IP core results in equivalent jitter performance. The preferred solution is to use the IOPLL, because using the Altera PHYLite IP core is resource intensive.