AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

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ID 683231
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines x
1.1. Implementing the Altera PHYLite Design 1.2. Mapping the Interface Signals 1.3. Performance Comparison 1.4. Use Case Examples 1.5. Altera GPIO to Altera PHYLite Design Example 1.6. Document Revision History
1.1. Implementing the Altera PHYLite Design x
1.1.1. Parameter Settings
1.4. Use Case Examples x
1.4.1. Use Case 1: Source Synchronous I/O Interface 1.4.2. Use Case 2: Driving Data from FPGA through GPIO to External Device 1.4.3. Use Case 3: Multiple-Speed Parallel Interfaces 1.4.4. Use Case 4: GPIO Interface Using 3.0V/2.5V I/O Standard 1.4.5. Use Case 5: Generating Output Clock through GPIO Output Pin
1.5. Altera GPIO to Altera PHYLite Design Example x
1.5.1. Simulation Diagrams 1.5.2. Design Verification
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

1.4.5. Use Case 5: Generating Output Clock through GPIO Output Pin

Example 5 describes the generation of an output clock through a GPIO output pin. The source of the output clock is from the transceiver SERDES recovered clock.
Figure 8. Recovered Clock from Transceiver Produced Through GPIO Interface

Generate the output clock through the PHYLite IP core if you use a regular I/O.

Figure 9. Recovered Clock Feeding Through I/O PLL to Generate Output Clock Using Dedicated Clock Out Pin

Figure 10. Recovered Clock Feeding Through Altera PHYLite IP Core to Generate Output Clock Using Regular GPIO Pin

Generating the recovered clock through a dedicated clock out pin from the IOPLL or through the Altera PHYLite IP core results in equivalent jitter performance. The preferred solution is to use the IOPLL, because using the Altera PHYLite IP core is resource intensive.

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