1.4.5. Use Case 5: Generating Output Clock through GPIO Output Pin
Generate the output clock through the PHYLite IP core if you use a regular I/O.
Generating the recovered clock through a dedicated clock out pin from the IOPLL or through the Altera PHYLite IP core results in equivalent jitter performance. The preferred solution is to use the IOPLL, because using the Altera PHYLite IP core is resource intensive.
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