Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents Locked

The locked signal port of the IP core for each PLL is as follows:

  • fPLL—pll_locked
  • I/O PLL—locked

The lock detection circuit provides a signal to the core logic. The signal indicates when the feedback clock has locked onto the reference clock both in phase and frequency.