Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents

10.7. Power Sequencing Considerations for Arria® 10 Devices

The Arria® 10 devices require a specific power-up and power-down sequence. This document describes several power management options and discusses proper I/O management during device power-up and power-down. Design your power supply solution to properly control the complete power sequence.

The requirements in this document must be followed to prevent unnecessary current draw to the FPGA device. Arria® 10 devices do not support 'Hot-Socketing' except under the conditions stated in the table below. The tables below also show what the unpowered pins can tolerate during power-up and power-down sequences.

Table 129.  Pin Tolerance – Power-Up/Power-Down'√' is Applicable; '-' is Not Applicable.
Power-Up Power-Down
Pin Type Tristate Drive to GND Drive to VCCIO Driven with < 1.1 Vp-p Tristate Drive to GND Drive to VCCIO Driven with < 1.1 Vp-p
3VIO banks - - - - -
LVDS I/O banks 54 - 54 -
Differential Transceiver pins - - - -
54 The maximum current allowed through any LVDS I/O bank pin when the device is unpowered or during power up/down conditions = 10 mA (refer to "LVDS I/O Pin Guidance for Unpowered FPGA Pins").