10.7. Power Sequencing Considerations for Intel® Arria® 10 Devices
The requirements in this document must be followed to prevent unnecessary current draw to the FPGA device. Intel® Arria® 10 devices do not support 'Hot-Socketing' except under the conditions stated in the table below. The tables below also show what the unpowered pins can tolerate during power-up and power-down sequences.
|Pin Type||Tristate||Drive to GND||Drive to VCCIO||Driven with < 1.1 Vp-p||Tristate||Drive to GND||Drive to VCCIO||Driven with < 1.1 Vp-p|
|LVDS I/O banks||√||√||√54||-||√||√||√54||-|
|Differential Transceiver pins||√||√||-||-||√||√||-||-|