Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 1/21/2022
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7.3.4.1. FPP Configuration Timing

Figure 153. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Figure 154. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.