Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

9.3. Performing BST

You can issue BYPASS, IDCODE, and SAMPLE JTAG instructions before, after, or during configuration without having to interrupt configuration.

To issue other JTAG instructions, follow these guidelines:

  • To perform testing before configuration, hold the nCONFIG pin low.
  • To perform BST during configuration, issue CONFIG_IO JTAG instruction to interrupt configuration. While configuration is interrupted, you can issue other JTAG instructions to perform BST. After BST is completed, issue the PULSE_NCONFIG JTAG instruction or pulse nCONFIG low to reconfigure the device.

The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on Intel® Arria® 10 devices do not affect JTAG boundary-scan or configuration operations. Toggling these pins does not disrupt BST operation (other than the expected BST behavior).

If you design a board for JTAG configuration of Intel® Arria® 10 devices, consider the connections for the dedicated configuration pins.

Note: For SoC devices, JTAG connections in the FPGA block and JTAG connections in the HPS block are chained to the Intel® Arria® 10 device. JTAG connections in the FPGA have higher priority over the JTAG connections in the HPS block.
Note: If you perform the HIGHZ JTAG instruction before or during configuration, you need to pull the nIO_PULLUP pin to high to disable the internal weak pull-up resistors in the I/O elements. If you perform this JTAG instruction during user mode, you can pull high or pull low the nIO_PULLUP pin.
Note: If you perform BST during user mode, you are not able to capture the correct values for the PR_ENABLE, CRC_ERROR, and CVP_CONFDONE pins when these pins are not used as user I/O pins.
Note: You can perform JTAG BST only when both nCONFIG and nSTATUS goes high after power-up.

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