Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 1/21/2022
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10.4.2.1.2. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is not Equal to 2'b11

The following timing diagram shows the IP core timing to access the voltage sensor when MD[1:0] is not equal to 2'b11.

Figure 185. Timing Diagram when MD[1:0] is not Equal to 2'b11


Procedure

  1. A low-to-high transition on the corectl signal enables the core access mode.
    Wait for a minimum of two clock cycles before proceeding to step 2.
  2. De-asserting the reset signal releases the voltage sensor from the reset state.
    Wait for a minimum two clock cycles before proceeding to step 3.
  3. Configure the voltage sensor by writing the configuration registers and asserting the coreconfig signal for eight clock cycles. The configuration register access mode is 8 bits and configuration data is shifted in serially.
  4. The coreconfig signal going low indicates the start of the conversion based on the configuration defined in the configuration register.
  5. Poll the eoc and eos status signals to check if conversion for the first channel defined by MD[1:0] is complete. Latch the output data on the dataout[5:0] signal at the falling edge of the eoc signal.
  6. Poll the eoc and eos status signals to check if conversion for the subsequent channels defined by MD[1:0] are complete. Latch the output data on the dataout[5:0] signal at the falling edge of the eoc signal.
  7. Repeat step 6 until the eos signal is asserted, indicating the completion of the conversion of one cycle on the channels specified by MD[1:0].
    1. Both the eoc and eos signals are asserted on the same clock cycle when the voltage sensor completes the conversion for the last channel.
    2. You can only interrupt the operation of the voltage sensor by writing into the configuration register after one cycle of the eos signal completes.
  8. When the sequence completes, and if the corectl and reset signals remain unchanged, the conversion repeats the same sequence again until corectl is 0 and reset is 1. If you want to measure other sequences, repeat step 2 to step 7.