Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 1/21/2022
Document Table of Contents

10.6. Power-On Reset Circuitry

The POR circuitry keeps the Intel® Arria® 10 device in the reset state until the power supply outputs are within the recommended operating range.

A POR event occurs when you power up the Intel® Arria® 10 device until all power supplies reach the recommended operating range within the maximum power supply ramp time, tRAMP . If tRAMP is not met, the Intel® Arria® 10 device I/O pins and programming registers remain tri-stated, during which device configuration could fail.

Figure 192. Relationship Between tRAMP and POR Delay

The Intel® Arria® 10 POR circuitry uses an individual detecting circuitry to monitor each of the configuration-related power supplies independently. The main POR circuitry is gated by the outputs of all the individual detectors. The main POR signal is asserted when the power starts to ramp up. This signal is released after the last ramp-up power reaches the POR trip level followed by a POR delay. You can select the fast or standard POR delay time by setting the MSEL pins.

For configuration via protocol (CvP), the total TRAMP must be less than 10 ms from the first power supply ramp-up to the last power supply ramp-up. Select a fast POR delay setting to allow sufficient time for the PCI Express* ( PCIe* ) link initialization and configuration.

In user mode, the main POR signal is asserted when any of the monitored power supplies go below its POR trip level. Asserting the POR signal forces the device into the reset state.

The POR circuitry checks the functionality of the I/O level shifters powered by the VCCPT and VCCPGM power supplies during power-up mode. The main POR circuitry waits for all the individual POR circuitries to release the POR signal before allowing the control block to start programming the device.

Figure 193. Simplified POR Diagram for Intel® Arria® 10 Devices