Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 1/21/2022
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4.1.5.1. Pin Mapping in Intel® Arria® 10 Devices

Table 28.  Mapping Between the Clock Input Pins, PLL Counter Outputs, and Clock Control Block Inputs for HSSI Column
Clock Fed by
inclk[0] PLL counters C0 and C2 from adjacent fPLLs.
inclk[1] PLL counters C1 and C3 from adjacent fPLLs.
inclk[2] and inclk[3] Any of the two dedicated clock pins on the same HSSI bank.
Table 29.  Mapping Between the Clock Input Pins, PLL Counter Outputs, and Clock Control Block Inputs for I/O ColumnOne counter can only be assigned to one inclk.
Clock Fed by
inclk[0] CLK_[2,3][A..L]_0p or any counters from adjacent I/O PLLs.
inclk[1] CLK_[2,3][A..L]_0n or any counters from adjacent I/O PLLs.
inclk[2] CLK_[2,3][A..L]_1p or any counters from adjacent I/O PLLs.
inclk[3] CLK_[2,3][A..L]_1n or any counters from adjacent I/O PLLs.