Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents

3.1.1. Features

The Intel® Arria® 10 variable precision DSP blocks support fixed-point arithmetic and floating-point arithmetic.

Features for fixed-point arithmetic:

  • High-performance, power-optimized, and fully registered multiplication operations
  • 18-bit and 27-bit word lengths
  • Two 18 x 19 multipliers or one 27 x 27 multiplier per DSP block
  • Built-in addition, subtraction, and 64-bit double accumulation register to combine multiplication results
  • Cascading 19-bit or 27-bit when pre-adder is disabled and cascading 18-bit when pre-adder is used to form the tap-delay line for filtering applications
  • Cascading 64-bit output bus to propagate output results from one block to the next block without external logic support
  • Hard pre-adder supported in 19-bit and 27-bit modes for symmetric filters
  • Internal coefficient register bank in both 18-bit and 27-bit modes for filter implementation
  • 18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder
  • Biased rounding support

Features for floating-point arithmetic:

  • A completely hardened architecture that supports multiplication, addition, subtraction, multiply-add, and multiply-subtract
  • Multiplication with accumulation capability and a dynamic accumulator reset control
  • Multiplication with cascade summation capability
  • Multiplication with cascade subtraction capability
  • Complex multiplication
  • Direct vector dot product
  • Systolic FIR filter