Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents

3.4.1. Input Register Bank

Table 23.  Input Register Bank
Fixed-Point Arithmetic Floating-Point Arithmetic
  • Data
  • Dynamic control signals
  • Two sets of delay registers
  • Data
  • Dynamic ACCUMULATE control signal

All the registers in the DSP blocks are positive-edge triggered and cleared on power up. Each multiplier operand can feed an input register or a multiplier directly, bypassing the input registers.

The following variable precision DSP block signals control the input registers within the variable precision DSP block:

  • CLK[2..0]
  • ENA[2..0]
  • ACLR[0]

In fixed-point arithmetic 18 x 19 mode, you can use the delay registers to balance the latency requirements when you use both the input cascade and chainout features.

The tap-delay line feature allows you to drive the top leg of the multiplier input, dataa_y0 and datab_y1 in fixed-point arithmetic 18 x 19 mode and dataa_y0 only in fixed-point arithmetic 27 x 27 mode, from the general routing or cascade chain.