5.5.1. I/O Element Structure in Intel® Arria® 10 Devices
The I/O elements (IOEs) in Intel® Arria® 10 devices contain a bidirectional I/O buffer and I/O registers to support a complete embedded bidirectional single data rate (SDR) or double data rate (DDR) transfer.
The IOEs are located in I/O columns within the core fabric of the Intel® Arria® 10 device.
Intel® Arria® 10 SX devices also have IOEs for the HPS.
The GPIO IOE register consists of the DDR register, the half rate register, and the transmitter delay chains for input, output, and output enable (OE) paths:
- You can take data from the combinatorial path or the registered path.
- Only the core clock clocks the data.
- The half rate clock routed from the core clocks the half rate register.
- The full rate clock from the core clocks the full rate register.