184.108.40.206. Manual Clock Switchover
In manual clock switchover mode, the extswitch signal controls whether inclk0 or inclk1 is selected as the input clock to the PLL. By default, inclk0 is selected.
A clock switchover event is initiated when the extswitch signal transitions from logic high to logic low, and being held low for at least three inclk cycles for the inclk being switched to.
You must bring the extswitch signal back high again to perform another switchover event. If you do not require another switchover event, you can leave the extswitch signal in a logic low state after the initial switch.
Pulsing the extswitch signal low for at least three inclk cycles for the inclk being switched to performs another switchover event.
If inclk0 and inclk1 are different frequencies and are always running, the extswitch signal minimum low time must be greater than or equal to three of the slower frequency inclk0 and inclk1 cycles.
You can delay the clock switchover action by specifying the switchover delay in the Altera IOPLL (for I/O PLL) and Arria 10 FPLL (for fPLL) IP cores. When you specify the switchover delay, the extswitch signal must be held low for at least three inclk cycles for the inclk being switched to plus the number of the delay cycles that has been specified to initiate a clock switchover.
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