Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents

2.12. Embedded Memory Blocks in Intel® Arria® 10 Devices Revision History

Date Version Changes
December 2017 2017.12.15
  • Updated the ECC Block Diagram for M20K Memory figure.
  • Removed the term "one-hot" fashion for byte enables operation. The term one-hot indicates that only one bit can be active at a time.
March 2017 2017.03.15
  • Rebranded as Intel.
  • Removed parity bit support for MLAB under the Error Correction Code (ECC) support feature in the Memory Features in Arria 10 Devices table.
  • Removed parity bit support for MLAB blocks in the Parity Bit topic.
October 2016 2016.10.31
  • Removed Address clock enable support for MLAB block.
December 2015 2015.12.14
  • Updated the number of M20K memory blocks for Arria 10 GX 660 from 2133 to 2131 and corrected the total RAM bit from 48,448 Kb to 48,408 Kb.
November 2015 2015.11.02
  • Updated the following topics: Embedded Memory Configurations for Single-port mode and Embedded Memory Configurations for Dual-port mode.
  • Updated the description in the Data Byte Output topic.
  • Updated the Embedded Memory Capacity and Distribution table.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.15 Updated links.
May 2015 2015.05.04
  • Updated Mega Wizard Plug-In manager to IP Core parameter editor.
  • Updated Megafunction to IP core.
August 2014 2014.08.18
  • Added a new timing diagram for output latch clear in ECC mode.
  • Added a note to clarify that for Intel® Arria® 10 devices, the Resource Property Editor and the TimeQuest Timing Analyzer report the location of the M20K block as EC_X<number>_Y<number>_N<number>
  • Updated the RAM bit value in M20K block for Arria 10 GX 660 and Arria 10 SX 660.
December 2013 2013.12.02 Initial release.