Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 10/25/2023
Document Table of Contents Guideline: I/O Standards Supported for I/O PLL Reference Clock Input Pin

The I/O PLL reference clock (REFCLK) input pin supports the following I/O standards only:

  • Single-ended I/O standards
  • LVDS

Arria® 10 devices support Differential HSTL and Differential SSTL input operation using LVDS input buffers. To support the electrical specifications of Differential HSTL or Differential SSTL signaling, assign the LVDS I/O standard to the REFCLK pin in the Quartus® Prime software.