Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 5/27/2022
Public
Download
Document Table of Contents

5.6.5.1.2. Synchronizer

The synchronizer is a one-bit wide and six-bit deep FIFO buffer that compensates for the phase difference between dpa_fast_clock—the optimal clock that the DPA block selects—and the fast_clock that the I/O PLLs produce. The synchronizer can only compensate for phase differences, not frequency differences, between the data and the receiver’s input reference clock.

An optional port, rx_fifo_reset, is available to the internal logic to reset the synchronizer. The synchronizer is automatically reset when the DPA first locks to the incoming data. Intel recommends that you use rx_fifo_reset to reset the synchronizer when the data checker indicates that the received data is corrupted.

Note: The synchronizer circuit is bypassed in non-DPA and soft-CDR mode.

Did you find the information on this page useful?

Characters remaining:

Feedback Message