Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 5/27/2022
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3.5.1.5.1. Mapping Systolic Mode User View to Variable Precision Block Architecture View

The following figure shows that the user view of the systolic FIR filter (a) can be implemented using the Intel® Arria® 10 variable precision DSP blocks (d) by retiming the register and restructuring the adder. Register B can be retimed into systolic registers at the chainin, dataa_y0 and dataa_x0 input paths as shown in (b). The end result of the register retiming is shown in (c). The summation of two multiplier results by restructuring the inputs and location of the adder are added to the chainin input by the chainout adder as shown in (d).

Figure 38. Mapping Systolic Mode User View to Variable Precision Block Architecture View

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