Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

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Date 1/21/2022
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5.6.6.6.2. IOPLL Parameter Values for External PLL Mode

The following examples show the clocking requirements to generate output clocks for LVDS SERDES IP core using the IOPLL IP core. The examples set the phase shift with the assumption that the clock and data are edge aligned at the pins of the device.

Note: For other clock and data phase relationships, Intel recommends that you first instantiate your LVDS SERDES IP core interface without using the external PLL mode option. Compile the IP cores in the Intel® Quartus® Prime software and take note of the frequency, phase shift, and duty cycle settings for each clock output. Enter these settings in the IOPLL IP core parameter editor and then connect the appropriate output to the LVDS SERDES IP cores.
Table 67.  Example: Generating Output Clocks Using an IOPLL IP core (Receiver in Non-DPA Mode) This table lists the parameter values that you can set in the IOPLL IP core parameter editor to generate three output clocks using an IOPLL IP core if you are using the non-DPA receiver.
Parameter

outclk0

(Connects as lvds_clk[0] to the ext_fclk port of LVDS SERDES IP core transmitter or receiver)

outclk1

(Connects as loaden[0] to the ext_loaden port of LVDS SERDES IP core transmitter or receiver)

outclk2

(Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP core)

Frequency

data rate

data rate/serialization factor

data rate/serialization factor

Phase shift

180°

[(deserialization factor – 1)/deserialization factor] x 360°

180/serialization factor

(outclk0 phase shift divided by the serialization factor)

Duty cycle

50%

100/serialization factor

50%

The calculations for phase shift, using the RSKM equation, assume that the input clock and serial data are edge aligned. Introducing a phase shift of 180° to sampling clock (outclk0) ensures that the input data is center-aligned with respect to the outclk0, as shown in the following figure.

Figure 115. Phase Relationship for External PLL Interface Signals


Table 68.  Example: Generating Output Clocks Using an IOPLL IP core (Receiver in DPA or Soft-CDR Mode)This table lists the parameter values that you can set in the IOPLL IP core parameter editor to generate four output clocks using an IOPLL IP core if you are using the DPA or soft-CDR receiver. The locked output port of IOPLL IP core must be inverted and connected to the pll_areset port of the LVDS SERDES IP core if you are using the DPA or soft-CDR receiver.
Parameter

outclk0

(Connects as lvds_clk[0] to the ext_fclk port of LVDS SERDES IP core transmitter or receiver)

outclk1

(Connects as loaden[0] to the ext_loaden port of LVDS SERDES IP core transmitter or receiver)

Not required for the soft-CDR receiver.

outclk2

(Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP core)

VCO Frequency

(Connects as phout[7:0] to the ext_vcoph[7:0] port of LVDS SERDES IP core)

Frequency

data rate

data rate/serialization factor

data rate/serialization factor

data rate

Phase shift

180°

[(deserialization factor - 1)/deserialization factor] x 360°

180/serialization factor

(outclk0 phase shift divided by the serialization factor)

Duty cycle

50%

100/serialization factor

50%

Table 69.  Example: Generating Output Clocks Using a Shared IOPLL IP core for Transmitter Spanning Multiple Banks Shared with Receiver Channels (Receiver in DPA or Soft-CDR Mode)This table lists the parameter values that you can set in the IOPLL IP core parameter editor to generate six output clocks using an IOPLL IP core. Use these settings if you use transmitter channels that span multiple banks shared with receiver channels in DPA or soft-CDR mode. The locked output port of IOPLL IP core must be inverted and connected to the pll_areset port of the LVDS SERDES IP core if you are using the DPA or soft-CDR mode.
Parameter

outclk0

(Connects as lvds_clk[0] to the ext_fclk port of LVDS SERDES IP core receiver)

outclk1

(Connects as loaden[0] to the ext_loaden port of LVDS SERDES IP core receiver)

Not required for the soft-CDR receiver.

outclk4

(Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP core)

VCO Frequency

(Connects as phout[7:0] to the ext_vcoph[7:0] port of LVDS SERDES IP core)

outclk2

(Connects as lvds_clk[1] to the ext_fclk port of LVDS SERDES IP core transmitter)

outclk3

(Connects as loaden[1] to the ext_loaden port of LVDS SERDES IP core transmitter)

Frequency

data rate

data rate/serialization factor

data rate/serialization factor

data rate

Phase shift

180°

[(deserialization factor - 1)/deserialization factor] x 360°

180/serialization factor

(outclk0 phase shift divided by the serialization factor)

Duty cycle

50%

100/serialization factor

50%