Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

3.6. Variable Precision DSP Blocks in Intel® Arria® 10 Devices Revision History

Document Version Changes
2021.08.13
  • Added the DSP Block Cascade Limit in Intel® Arria® 10 Devices topic.
  • Removed the statements about the number of DSP blocks you can cascade as systolic FIR structure in the following topics:
    • 18-bit Systolic FIR Mode
    • 27-Bit Systolic FIR Mode
  • In the 27-Bit Systolic FIR Mode topic, removed the "Systolic registers are not required in this mode" statement. The registers are not available in the 27-bit systolic FIR mode.
Date Version Changes
March 2017 2017.03.15
  • Rebranded as Intel.
  • Changed subtraction from x-y to y-x.
December 2015 2015.11.14
  • Corrected the number of DSP blocks for Arria 10 GX 660 from 1688 to 1687 in the table listing floating-point arithmetic resources.
November 2015 2015.11.02
  • Update resource count for Arria 10 GX 320, GX 480, GX 660, SX 320, SX 480, a SX 660 devices in Number of Multipliers in Intel® Arria® 10 Devices table.
  • Updated the Input Register Bank table to specify input register bank for dynamic control signal in floating-point arithmetic is only applicable for Dynamic ACCUMULATE control signal.
  • Clarified that 18 x19 systolic FIR mode, there are 7-bits overhead and 37-bits result.
  • Updated the number of supported cascaded DSP blocks for 18-bit and 27-bit systolic FIR modes.
  • Changed instances of Quartus II to Quartus Prime
May 2015 2015.05.04
  • Update Chainin and Chainout support for all Floating Point modes in Supported Combinations of Operational Modes and Features for Variable Precision DSP Block in Intel® Arria® 10 Devices table.
  • Added steps to retrieve design templates for Independent Multiplier Mode, Multiplier Adder Sum Mode, and Systolic FIR Mode.
  • Added Arria 10 Native Floating Point DSP IP core in Operational Modes table.
January 2015 2015.01.23
  • Added information for primitive DSP.
  • Update Supported Combinations of Operational Modes and Features for Variable Precision DSP Block in Intel® Arria® 10 Devices table with the column title Supported Operation Instance.
  • Update resource for Single Precision Floating Point Adders in Number of Multipliers in Intel® Arria® 10 Devices table.
  • Removed double accumulation registers are set statically in the programming file statement in Accumulator for Fixed-Point Arithmetic section.
  • Added ALTERA_FP_FUNCTIONS in the list of Quartus II DSP IP for floating-point arithmetic.
  • Added clarification on operational modes supported for delay registers in fixed-point arithmetic.
  • Added clarification that both top and bottom internal coefficient and pre-adder must be enabled if these features are being used.
August 2014 2014.08.18
  • Added floating-point arithmetic.
  • Added Dynamic ACCUMULATE, Dynamic LOADCONST, Dynamic SUB, Dynamic NEGATE to variable precision DSP blocks operational modes.
  • Added top delay registers and bottom delay registers along the input cascade chain.
  • Added the variable precision DSP block signals that control the pipeline registers within the variable precision DSP block.
  • Added condition that when both pre-adders within the same DSP block are used, they must share the same operation type (either addition or subtraction).
  • Updated 55-bit adder.
  • Added 38-bit adder.
  • Updated two 18 x 19 modes—where the adder is bypassed.
  • Updated Decimation to Decimation + Accumulate.
  • Added Decimation + Chainout Adder for accumulator functions and dynamic control signals.
  • Added 27 (signed or unsigned) x 27 (signed or unsigned) configuration with 1 multiplier per block.
  • Removed the chainout adder or accumulator from one sum of two 18 x 19 multipliers with one variable precision DSP block and one 18 x 18 multiplication summed with 36-Bit input mode block diagram.
  • Updated the basic FIR filter equation.
  • Added mapping systolic mode user view to variable precision block architecture view.
  • Added systolic registers are not required in 27-bit systolic FIR mode.
December 2013 2013.12.02 Initial release.

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